The increasing complexity of integrated circuits and especially the introduction of multiple cores (processors) within a single integrated circuit forced integrated circuit designers to develop deep pipe-lined interconnects as well as to try and re-use previously designed cores.
The re-use must take into account that various cores, peripherals and memory units are adapted to operate at different frequencies and/or using buses that differ from each other by their width.
Connecting a high speed core via a data rate converter and a deep pipelined crossbar to a slower memory unit may cause data rate converter overflow as well as inefficient usage of the pipeline.
There is a need to provide a device and method for scheduling data transactions over a deep pipelined component.